[{"data":1,"prerenderedAt":45},["ShallowReactive",2],{"publications-liblisa-oopsla24":3,"papers-liblisa-oopsla24-01-introduction":32},{"id":4,"title":5,"authors":6,"awards":7,"bibtex":8,"body":9,"date":20,"description":15,"extension":21,"link":22,"meta":23,"navigation":24,"path":25,"pdf":26,"seo":27,"slug":28,"stem":29,"venue":30,"__hash__":31},"publications\u002Fpublications\u002Fliblisa-oopsla24.md","libLISA: Instruction Discovery and Analysis on x86-64","Jos Craaijo, Freek Verbeek, Binoy Ravindran",null,"@article{craaijo2024liblisa,\n  author = {Craaijo, Jos and Verbeek, Freek and Ravindran, Binoy},\n  title = {libLISA: Instruction Discovery and Analysis on x86-64},\n  year = {2024},\n  issue_date = {October 2024},\n  publisher = {Association for Computing Machinery},\n  address = {New York, NY, USA},\n  volume = {8},\n  number = {OOPSLA2},\n  url = {https:\u002F\u002Fdoi.org\u002F10.1145\u002F3689723},\n  doi = {10.1145\u002F3689723},\n  journal = {Proc. ACM Program. Lang.},\n  month = oct,\n  articleno = {283},\n  numpages = {29},\n  keywords = {instruction semantics, instruction enumeration, synthesis}\n}\n",{"type":10,"value":11,"toc":16},"minimark",[12],[13,14,15],"p",{},"Even though heavily researched, a full formal model of the x86-64 instruction set is still not available. We present libLISA, a tool for automated discovery and analysis of the ISA of a CPU. This produces the most extensive formal x86-64 model to date, with over 118000 different instruction groups. The process requires as little human specification as possible: specifically, we do not rely on a human-written (dis)assembler to dictate which instructions are executable on a given CPU, or what their in- and outputs are. The generated model is CPU-specific: behavior that is “undefined” is synthesized for the current machine. Producing models for five different x86-64 machines, we mutually compare them, discover undocumented instructions, and generate instruction sequences that are CPU-specific. Experimental evaluation shows that we enumerate virtually all instructions within scope, that the instructions’ semantics are correct w.r.t. existing work, and that we improve existing work by exposing bugs in their handwritten models.",{"title":17,"searchDepth":18,"depth":18,"links":19},"",2,[],"2024-10-20","md","https:\u002F\u002F2024.splashcon.org\u002Ftrack\u002Fsplash-2024-oopsla#event-overview",{},true,"\u002Fpublications\u002Fliblisa-oopsla24","\u002Ffiles\u002Fliblisa2024.pdf",{"title":5,"description":15},"liblisa-oopsla24","publications\u002Fliblisa-oopsla24","OOPSLA'24","d-2xqRiGEx9J763VU4sUFN1PvG_NX8MmqYk4AdsbW9Y",{"id":33,"title":34,"body":7,"date":7,"description":7,"extension":35,"html":36,"meta":37,"navigation":24,"next":38,"path":41,"previous":7,"seo":42,"slug":7,"stem":43,"__hash__":44},"papers\u002Fpublications\u002Fliblisa-oopsla24\u002F01-introduction.html","Introduction","html","\u003Cstyle>\u002F* Alignment *\u002F\nmtable.right-align mtd,\nmtable mtd.right-align,\nmtable.left-align mtd.right-align,\nmtable.aligned mtd:nth-child(odd) {\n  justify-items: end;\n  text-align: right;\n}\nmtable.cases mtd,\nmtable.left-align mtd,\nmtable mtd.left-align,\nmtable.aligned mtd:nth-child(even),\nmath:is(:not([display])) > mtable.multiline-equation mtd {\n  justify-items: start;\n  text-align: left;\n}\nmtable.cases mtd,\nmtable.aligned mtd,\nmtable mtd.flushed,\nmtable mtd.left-flush {\n  padding-left: 0;\n}\nmtable.cases mtd,\nmtable.aligned mtd,\nmtable mtd.flushed,\nmtable mtd.right-flush {\n  padding-right: 0;\n}\n\n\u002F* Tables *\u002F\nmtable {\n  math-style: inherit;\n}\nmtd {\n  math-depth: auto-add;\n  math-style: compact;\n  math-shift: compact;\n}\n\n\u002F* Equations *\u002F\nmtable.multiline-equation mtd {\n  math-depth: inherit;\n  math-style: inherit;\n  math-shift: inherit;\n  padding: 0;\n}\nmath > mtable.multiline-equation mtr:not(:last-child) mtd {\n  padding-bottom: 0.5em;\n}\n\n\u002F* Fractions *\u002F\nmfrac {\n  padding-inline: 0;\n  margin-inline: 0.1em;\n}\n\n\u002F* Accents *\u002F\nmover[accent=\"true\" i] > :first-child {\n  font-feature-settings: \"dtls\";\n}\nmover.dotted[accent=\"true\" i] > :first-child {\n  font-feature-settings: \"dtls\" 0;\n}\n\n\u002F* Other rules for scriptlevel, displaystyle and math-shift *\u002F\nmunder > :nth-child(2),\nmunderover > :nth-child(2) {\n  math-shift: compact\n}\nmunder[accentunder=\"true\" i] > :not(:first-child),\nmover[accent=\"true\" i] > :not(:first-child) {\n  math-depth: inherit;\n  math-style: inherit;\n  math-shift: inherit;\n}\u003C\u002Fstyle>\u003Cdiv id=\"previous-page\" style=\"display: none\">\u003C\u002Fdiv>\u003Cdiv id=\"next-page\" style=\"display: none\">\u003Ca href=\"02-overview#loc-1\">Overview\u003C\u002Fa>\u003C\u002Fdiv>\u003Ch2 id=\"introduction\">1 Introduction\u003C\u002Fh2>\u003Cp>A proper understanding of the microarchitectural behavior of the instructions that can be executed on a CPU is crucial for any effort related to binaries. Binary verification, binary security analysis, binary patching, decompilation, and compiler construction\u002Fverification each require – first and foremost – a semantic model of each instruction that is executed by the binary. Semantics are needed that are \u003Cem>trustworthy\u003C\u002Fem>, \u003Cem>executable\u003C\u002Fem> and \u003Cem>complete\u003C\u002Fem>.\u003C\u002Fp>\u003Cp>Even with all the research efforts that have been put into this topic \u003Cspan id=\"loc-1\">[\u003C\u002Fspan>\u003Ca href=\"08-bibliography#loc-3\" role=\"doc-biblioref\">1\u003C\u002Fa>–\u003Ca href=\"08-bibliography#loc-8\" role=\"doc-biblioref\">7\u003C\u002Fa>], to this day there is no complete and trustworthy model of the x86-64 architecture. This is caused by the sheer complexity of the x86-64 architecture: the informal specification found in Intel manuals is roughly 4700 pages, and even these are known to be not trustworthy [\u003Ca href=\"08-bibliography#loc-4\" role=\"doc-biblioref\">2\u003C\u002Fa>]. Specifications of CPU architectures often rely heavily on manual work, which is error-prone and labor-intensive. This situation becomes even more dire when taking into account that different x86-64 machines will behave differently: not only can they have different instruction sets, but behavior is also allowed to be undefined, in which case the same instruction has different behavior on different machines.\u003C\u002Fp>\u003Cp>Accurate semantics must inherently be CPU-specific. Consider for example the assembly program in \u003Ca href=\"#loc-2\">Figure 1\u003C\u002Fa>. Nowhere in the literature of the current state-of-the-art can semantics be found that accurately describe the behavior of this function. This is because the value of the overflow flag after RCL is undefined. For example, on an AMD 3900X the code will execute the SYSCALL when RAX is 0x80, while on an Intel Xeon Silver 4110 the SYSCALL is never executed. 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\u003C\u002Fspan>\u003C\u002Fstrong> An example of a function in an x86-64 binary. For convenience, the output of the objdump disassembler is listed next to the bytes. The function moves its first argument RDI into RAX, clears RDI with an XOR, then performs a rotate-with-carry (rcl) of 9 on RAX, and finally conditionally jumps (jno) to the end of the function if the overflow flag is unset, or executes a syscall before returning otherwise.\u003C\u002Fem>\u003C\u002Fp>\u003C\u002Ffigure>\u003Cp>In this paper we introduce \u003Cspan style=\"font-variant-caps: small-caps\">libLISA\u003C\u002Fspan>: a tool that can fully automatically scan a large part of the instruction space of an x86-64 CPU, discover instructions, and synthesize their semantics. The result is \u003Cem>CPU-specific\u003C\u002Fem> semantics, i.e., semantics that define what the current CPU actually does even in the case of instructions whose behavior is considered “undefined” by manually written specifications. Both discovery and synthesis are completely automated. We rely on as little human specification as possible. Notably, we do not rely on a handwritten disassembler to dictate which bitstrings are valid instructions.\u003C\u002Fp>\u003Cp>For each CPU, the entire space of possible executable bitstrings is grouped into \u003Cem>encodings\u003C\u002Fem>: bitstrings where certain bits are found to be indicating a certain \u003Cem>operand\u003C\u002Fem>. A hypothetical example could be the encoding 00\u003Cspan style=\"text-decoration: underline\">a\u003C\u002Fspan>1010\u003Cspan style=\"text-decoration: underline\">aa\u003C\u002Fspan>0 where the three \u003Cspan style=\"text-decoration: underline\">a\u003C\u002Fspan> bits of the bitstring are found to be indicating an input register. The intuition is that each encoding models a group of actual instructions (i.e., bitstrings) that each perform the same operation but on different operands. Note that there is no relation between the concept of encodings (which are \u003Cem>derived\u003C\u002Fem> bottom-up) and existing concepts such as mnemonics or instruction variants (which are \u003Cem>manually created\u003C\u002Fem> top-down). Subsequently, we try to synthesize semantics for each encoding. The result is a partial \u003Cem>mapping from encodings to semantics\u003C\u002Fem>: partial, as synthesis may fail.\u003C\u002Fp>\u003Cp>We have run \u003Cspan style=\"font-variant-caps: small-caps\">libLISA\u003C\u002Fspan> on five different x86-64 CPU architectures. This enumerates roughly 118000 encodings per architecture; this number differs based on which x86-64 extensions the CPU supports. For roughly 88% of all encodings we can synthesize semantics. One run takes roughly three to four months. We have exposed executable instructions that were \u003Cem>undocumented\u003C\u002Fem> and synthesized their semantics: these are executable bitstrings that are not in the AMD and Intel manuals and that are unknown to both assemblers and disassemblers. We mutually compare the five x86-64 machines by partitioning the set of encodings based on whether their semantics are equivalent. This allows one to construct instruction sequences that behave differently on different architectures, e.g., that behave benign on an AMD Ryzen R9 3900X but behave maliciously on an Intel Core i9-13900.\u003C\u002Fp>\u003Cp>Natural questions to ask are: “Did we find all executable instructions?” and “Are the generated semantics correct?” We provide extensive evaluation of \u003Cspan style=\"font-variant-caps: small-caps\">libLISA\u003C\u002Fspan>’s output in \u003Ca href=\"05-results#loc-1\">Section 5\u003C\u002Fa>, but it is important to note that there is no ground truth. Instruction semantics are notoriously subtle, so even if we could manually check the semantics for over 100000 encodings, that kind of verification effort would in itself be highly error-prone and untrustworthy. We therefore evaluate these questions relative to best-effort oracles (e.g., by enumerating all instructions in binaries such as ssh and gcc) and relative to the most extensive x86-64 specification currently available in related work cite{dasgupta2019}. This shows that we find virtually all instructions in scope.\u003C\u002Fp>\u003Cp>To the best of our knowledge, the work of Dasgupta et al. is the most extensive specification of x86-64 userspace instructions currently available cite{dasgupta2019}. Their work is based on the earlier work of Heule et al. [\u003Ca href=\"08-bibliography#loc-4\" role=\"doc-biblioref\">2\u003C\u002Fa>] on Strata which provides a way to synthesize the semantics for 1795 instruction variants. Dasgupta et al.\u003Cbr>manually extend this work to 3155 instruction variants, which required a manual effort of eight man-months [\u003Ca href=\"08-bibliography#loc-3\" role=\"doc-biblioref\">1\u003C\u002Fa>]. That set of instruction variants is not complete: \u003Cspan style=\"font-variant-caps: small-caps\">libLISA\u003C\u002Fspan> enumerates 11152 encodings that cannot be mapped to instruction variants from this set. A mutual comparison between the semantics generated by \u003Cspan style=\"font-variant-caps: small-caps\">libLISA\u003C\u002Fspan> and their semantics exposed bugs: cases where their semantics did not represent what actually happens when instructions are executed on a CPU. Moreover, there are notable differences: 1.) \u003Cspan style=\"font-variant-caps: small-caps\">libLISA\u003C\u002Fspan> is fully automated, 2.) \u003Cspan style=\"font-variant-caps: small-caps\">libLISA\u003C\u002Fspan> \u003Cem>discovers\u003C\u002Fem> the instructions instead of leveraging a pre-existing set of instruction variants taken from a handwritten assembler, and 3.) \u003Cspan style=\"font-variant-caps: small-caps\">libLISA\u003C\u002Fspan> generates CPU-specific semantics. A more thorough comparison to the state-of-the-art can be found in \u003Ca href=\"03-related-work#loc-1\">Section 3\u003C\u002Fa>.\u003C\u002Fp>\u003Cp>We restrict the enumeration scope of our work to x86-64 userspace instructions. We choose x86-64, as it is a complex and widely-used instruction set architecture with variable length instructions between 1 and 15 bytes. Other modern architectures such as ARM or RISC-V have significantly simpler fixed-length or mostly fixed-length instructions. Additionally, there is no complete and trustworthy model of the x86-64 architecture.\u003C\u002Fp>\u003Cp>We restrict instruction prefixes to a limited set of allowed prefixes. We do not analyze concurrency, memory ordering or timing behavior. We also consider instructions using segment selectors and segment descriptors out-of-scope, as well as instructions that produce an undefined instruction exception (e.g., UD). Note that an “undefined instruction exception” is not in any way related to an “instruction with undefined behavior”. In \u003Ca href=\"02-overview#loc-7\">Section 2.2.1\u003C\u002Fa> we define a clear and unambiguous scope in more detail.\u003C\u002Fp>\u003Cp>To summarize, this paper contributes:\u003C\u002Fp>\u003Col>\u003Cli>a method for automated discovery and analysis of the ISA of a CPU;\u003C\u002Fli>\u003Cli>an implementation of this method, called \u003Cspan style=\"font-variant-caps: small-caps\">libLISA\u003C\u002Fspan>, for CPUs implementing the x86-64 architecture; and\u003C\u002Fli>\u003Cli>an extensive evaluation concerning completeness, correctness and the relation between the output of \u003Cspan style=\"font-variant-caps: small-caps\">libLISA\u003C\u002Fspan> and the state-of-the-art.\u003C\u002Fli>\u003C\u002Fol>",{},{"url":39,"title":40},"02-overview","Overview","\u002Fpublications\u002Fliblisa-oopsla24\u002F01-introduction",{"title":34},"publications\u002Fliblisa-oopsla24\u002F01-introduction","EW7PHMn0izZ84AjL5yEk0Ljlx5tANFGDDOc_5K-t9NA",1787004871380]