[{"data":1,"prerenderedAt":57},["ShallowReactive",2],{"publications-sem86-qrs26":3,"papers-sem86-qrs26-03-implementation":40},{"id":4,"title":5,"authors":6,"awards":7,"bibtex":11,"body":12,"date":27,"description":28,"extension":29,"link":30,"meta":31,"navigation":32,"path":33,"pdf":34,"seo":35,"slug":36,"stem":37,"venue":38,"__hash__":39},"publications\u002Fpublications\u002Fsem86-qrs26.md","Sem86: A Full-System Emulator Without Hard-Coded Semantics","Jos Craaijo, Freek Verbeek, Binoy Ravindran",[8],{"name":9,"url":10},"Best Presentation Award","https:\u002F\u002Fqrs26.techconf.org\u002Ftrack\u002Faward_presentation","",{"type":13,"value":14,"toc":24},"minimark",[15],[16,17,18,19,23],"p",{},"Emulation can be used to run legacy software, analyze malware in a sandboxed environment, or run software compiled for different architectures.\nAn emulator is based on instruction semantics.\nThere is, however, not a single instruction semantics to be followed, as x86 allows undefined behavior.\nIn order to make accurate CPU-specific emulators,\nwe argue the need for an emulator that can easily switch between different semantics.\nHowever, all existing emulators contain hard-coded semantics.\nWe present Sem86, an x86 emulator that loads semantics at runtime from data in an input file.\nWe implement all necessary hardware needed to emulate typical x86 operating systems such as Windows 98, Windows XP and Windows 7.\nAdditionally, we implement a sound card, network card and support for high-resolution display output.\nSem86 can automatically ",[20,21,22],"em",{},"bisect"," instruction execution to determine at which point different semantics would diverge.\nWe demonstrate this by constructing a toy malware example that exploits undefined instruction behavior to detect whether it is running in an emulator,\nand show that Sem86 can pinpoint the exact instruction that is used.",{"title":11,"searchDepth":25,"depth":25,"links":26},2,[],"2026-07-22","Emulation can be used to run legacy software, analyze malware in a sandboxed environment, or run software compiled for different architectures.\nAn emulator is based on instruction semantics.\nThere is, however, not a single instruction semantics to be followed, as x86 allows undefined behavior.\nIn order to make accurate CPU-specific emulators,\nwe argue the need for an emulator that can easily switch between different semantics.\nHowever, all existing emulators contain hard-coded semantics.\nWe present Sem86, an x86 emulator that loads semantics at runtime from data in an input file.\nWe implement all necessary hardware needed to emulate typical x86 operating systems such as Windows 98, Windows XP and Windows 7.\nAdditionally, we implement a sound card, network card and support for high-resolution display output.\nSem86 can automatically bisect instruction execution to determine at which point different semantics would diverge.\nWe demonstrate this by constructing a toy malware example that exploits undefined instruction behavior to detect whether it is running in an emulator,\nand show that Sem86 can pinpoint the exact instruction that is used.","md","https:\u002F\u002Fqrs26.techconf.org\u002F",{},true,"\u002Fpublications\u002Fsem86-qrs26","\u002Ffiles\u002Fsem86.pdf",{"title":5,"description":28},"sem86-qrs26","publications\u002Fsem86-qrs26","QRS'26","2isYelaLp7jOW_ygpxJBHzUdEprIalEWZTRkgsYVd-U",{"id":41,"title":42,"body":43,"date":43,"description":43,"extension":44,"html":45,"meta":46,"navigation":32,"next":47,"path":50,"previous":51,"seo":54,"slug":43,"stem":55,"__hash__":56},"papers\u002Fpublications\u002Fsem86-qrs26\u002F03-implementation.html","Implementation",null,"html","\u003Cstyle>\u002F* Alignment *\u002F\nmtable.right-align mtd,\nmtable mtd.right-align,\nmtable.left-align mtd.right-align,\nmtable.aligned mtd:nth-child(odd) {\n  justify-items: end;\n  text-align: right;\n}\nmtable.cases mtd,\nmtable.left-align mtd,\nmtable mtd.left-align,\nmtable.aligned mtd:nth-child(even),\nmath:is(:not([display])) > mtable.multiline-equation mtd {\n  justify-items: start;\n  text-align: left;\n}\nmtable.cases mtd,\nmtable.aligned mtd,\nmtable mtd.flushed,\nmtable mtd.left-flush {\n  padding-left: 0;\n}\nmtable.cases mtd,\nmtable.aligned mtd,\nmtable mtd.flushed,\nmtable mtd.right-flush {\n  padding-right: 0;\n}\n\n\u002F* Tables *\u002F\nmtable {\n  math-style: inherit;\n}\nmtd {\n  math-depth: auto-add;\n  math-style: compact;\n  math-shift: compact;\n}\n\n\u002F* Equations *\u002F\nmtable.multiline-equation mtd {\n  math-depth: inherit;\n  math-style: inherit;\n  math-shift: inherit;\n  padding: 0;\n}\nmath > mtable.multiline-equation mtr:not(:last-child) mtd {\n  padding-bottom: 0.5em;\n}\n\n\u002F* Fractions *\u002F\nmfrac {\n  padding-inline: 0;\n  margin-inline: 0.1em;\n}\n\n\u002F* Accents *\u002F\nmover[accent=\"true\" i] > :first-child {\n  font-feature-settings: \"dtls\";\n}\nmover.dotted[accent=\"true\" i] > :first-child {\n  font-feature-settings: \"dtls\" 0;\n}\n\n\u002F* Other rules for scriptlevel, displaystyle and math-shift *\u002F\nmunder > :nth-child(2),\nmunderover > :nth-child(2) {\n  math-shift: compact\n}\nmunder[accentunder=\"true\" i] > :not(:first-child),\nmover[accent=\"true\" i] > :not(:first-child) {\n  math-depth: inherit;\n  math-style: inherit;\n  math-shift: inherit;\n}\u003C\u002Fstyle>\u003Cdiv id=\"previous-page\" style=\"display: none\">\u003Ca href=\"\u002Fpublications\u002Fsem86-qrs26\u002F02-related-work#loc-1\">Related Work\u003C\u002Fa>\u003C\u002Fdiv>\u003Cdiv id=\"next-page\" style=\"display: none\">\u003Ca href=\"\u002Fpublications\u002Fsem86-qrs26\u002F04-evaluation#loc-1\">Evaluation\u003C\u002Fa>\u003C\u002Fdiv>\u003Ch2 id=\"loc-1\">3 Implementation\u003C\u002Fh2>\u003Cp>In this section we describe the implementation of \u003Cspan style=\"font-variant-caps: small-caps\">Sem86\u003C\u002Fspan>. We aim to build an emulator that is capable of booting real-world operating systems, such as Windows 98, XP and 7, loading semantics at runtime from an input file. Booting these operating systems requires executing hundreds of millions (Windows 98) up to tens of billions of instructions (Windows 7). Therefore, emulation performance is extremely important.\u003C\u002Fp>\u003Cp>\u003Cspan style=\"font-variant-caps: small-caps\">Sem86\u003C\u002Fspan> provides implementations of all necessary hardware to run normal operating systems. This includes PIT, PIC, CMOS and PS\u002F2 devices, PCI, a VBE-compatible VGA card, as well as optional hardware such as the ES1370 sound card and the and the NE2000 network card. We provide support for IDE disks, ATAPI CD-ROM drives, and floppy disks. For more modern operating systems, basic APIC support is also available.\u003C\u002Fp>\u003Cp>Instruction semantics are loaded from a data file at runtime. Other aspects of the architecture, such as the execution loop, paging, control registers, interrupt handling and system hardware are not specified in the semantics, and are hard coded in the emulator itself. While this reduces the expressivity of the semantics, it makes it possible to implement performance optimizations such as the fast memory technique or caching.\u003C\u002Fp>\u003Ch3>3.1 Semantics\u003C\u002Fh3>\u003Cp>An emulator requires (1) a mapping from bitstrings to semantics, i.e., an \u003Cem>instruction decoder\u003C\u002Fem>, and (2) an intermediate language in which semantics can be specified.\u003C\u002Fp>\u003Ch4>3.1.1 Instruction Decoding\u003C\u002Fh4>\u003Cp>x86 instruction decoding typically requires an expressive language: since x86 has variable-length instructions, extra instruction bytes may need to be fetched during decoding. It is not possible to fetch all potentially-needed instruction bytes in advance, as page faults can reveal how far ahead the instruction decoder is fetching bytes.\u003C\u002Fp>\u003Cp>Additionally, x86 instructions can use \u003Cem>prefixes\u003C\u002Fem>: bytes that can be prefixed once or multiple times to the instruction bitstring. Prefixes can, for example, affect register operands, change address- and operand size or override the segment register used by a memory access. There are even corner-cases where some prefixes behave differently on different CPUs \u003Cspan id=\"loc-2\">[\u003C\u002Fspan>\u003Ca href=\"\u002Fpublications\u002Fsem86-qrs26\u002F06-bibliography#loc-21\" role=\"doc-biblioref\">23\u003C\u002Fa>]. Thus, instruction decoding should not be hard-coded.\u003C\u002Fp>\u003Cp>Our implementation instead uses \u003Cem>bitpatterns\u003C\u002Fem> to match instructions. A bitpattern is a sequence of fixed bits (0, 1) and parts (a, b, c, …). An instruction bitstring is decoded by matching it against the bitpattern. The result of successful decoding is a mapping of parts to matched values.\u003C\u002Fp>\u003Cfigure>\u003Cdiv>\u003Cdiv>Example 1\u003C\u002Fdiv>\u003Cdiv>\u003Cp>The bitpattern \u003Ccode>IMUL\u003C\u002Fcode> instruction is \u003Ccode>00001111 10101111 11\u003Cspan style=\"text-decoration: underline\">bbb\u003C\u002Fspan>\u003Cspan style=\"text-decoration: underline\">aaa\u003C\u002Fspan>\u003C\u002Fcode>. Here, the parts \u003Cspan style=\"text-decoration: underline\">bbb\u003C\u002Fspan> and \u003Cspan style=\"text-decoration: underline\">aaa\u003C\u002Fspan> represent registers.\u003C\u002Fp>\u003Cp>To decode an instruction, for example \u003Ccode>00001111 10101111 11001010\u003C\u002Fcode>, we first verify that all fixed bits match the instruction. Then, we compute a mapping of parts to their corresponding values. For this example, part \u003Ccode>aaa\u003C\u002Fcode> is \u003Ccode>010\u003C\u002Fcode> and part \u003Ccode>bbb\u003C\u002Fcode> is \u003Ccode>001\u003C\u002Fcode>.\u003C\u002Fp>\u003C\u002Fdiv>\u003C\u002Fdiv>\u003C\u002Ffigure>\u003Cp>To decode instruction prefixes, we use finite state automata to compute a \u003Cem>shortest equivalent prefix sequence\u003C\u002Fem>. We then add separate bitpatterns and semantics for each possible combination of prefixes.\u003C\u002Fp>\u003Cfigure>\u003Cdiv>\u003Cdiv>Example 2\u003C\u002Fdiv>\u003Cdiv>\u003Cp>The \u003Ccode>IMUL\u003C\u002Fcode> instruction may optionally take a data-size override prefix (\u003Ccode>66\u003C\u002Fcode>) which reduces operand sizes to 16-bit instead of 32-bit (or vice versa when the CPU is running in 16-bit mode). This means that there will be two entries for this instruction: one with a data-size override prefix (the byte sequence \u003Ccode>66\u003C\u002Fcode>), and one without (the empty byte sequence \u003Cmath>\u003Cmi>𝜀\u003C\u002Fmi>\u003C\u002Fmath>). Each will have a state machine to map all possible equivalent prefix sequences:\u003C\u002Fp>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cmath display=\"block\">\u003Cmrow>\u003Cmo>{\u003C\u002Fmo>\u003Cmrow>\u003Cmn>66\u003C\u002Fmn>\u003Cmo>,\u003C\u002Fmo>\u003Cmtext>662E\u003C\u002Fmtext>\u003Cmo>,\u003C\u002Fmo>\u003Cmtext>2E66\u003C\u002Fmtext>\u003Cmo>,\u003C\u002Fmo>\u003Cmtext>3E66\u003C\u002Fmtext>\u003Cmo>,\u003C\u002Fmo>\u003Cmi>…\u003C\u002Fmi>\u003C\u002Fmrow>\u003Cmo>}\u003C\u002Fmo>\u003C\u002Fmrow>\u003Cmo stretchy=\"false\">↦\u003C\u002Fmo>\u003Cmn>66\u003C\u002Fmn>\u003C\u002Fmath>\u003Cmath display=\"block\">\u003Cmrow>\u003Cmo>{\u003C\u002Fmo>\u003Cmrow>\u003Cmi>𝜀\u003C\u002Fmi>\u003Cmo>,\u003C\u002Fmo>\u003Cmtext>2E\u003C\u002Fmtext>\u003Cmo>,\u003C\u002Fmo>\u003Cmtext>3E\u003C\u002Fmtext>\u003Cmo>,\u003C\u002Fmo>\u003Cmi>…\u003C\u002Fmi>\u003C\u002Fmrow>\u003Cmo>}\u003C\u002Fmo>\u003C\u002Fmrow>\u003Cmo stretchy=\"false\">↦\u003C\u002Fmo>\u003Cmi>𝜀\u003C\u002Fmi>\u003C\u002Fmath>\u003Cp>\u003Cbr>\u003C\u002Fp>\u003Cp>For example, when encountering an instruction prefixed with \u003Ccode>2E\u003C\u002Fcode>, we first reduce this to the empty byte sequence \u003Cmath>\u003Cmi>𝜀\u003C\u002Fmi>\u003C\u002Fmath> (according to the mapping provided by the finite state machine), and then match the rest of the instruction bitstring against the bitpattern.\u003C\u002Fp>\u003C\u002Fdiv>\u003C\u002Fdiv>\u003C\u002Ffigure>\u003Cp>Even though this approach is much less expressive than Turing-complete languages typically used for instruction decoding, it is sufficient to represent all x86 instructions. The downside of this approach is that it is not as compact as hand-crafted solutions: a single instruction form like \u003Ccode>IMUL\u003C\u002Fcode> may be encoded with dozens of different finite state machines and bitpatterns. In practice this is not a problem, as caching and JIT compilation mean that instruction decoding plays no role in emulator performance.\u003C\u002Fp>\u003Ch4>3.1.2 Intermediate Language\u003C\u002Fh4>\u003Cp>We encode instruction semantics in a simple intermediate language, of which the grammar is shown in \u003Ca href=\"#loc-3\">Figure 1\u003C\u002Fa>. The grammar consists of assignments, if-statements, memory- and port I\u002FO accesses, segment descriptors loads, and various exceptional early returns. All values are 128-bit integers, which means the semantics do not require typing. Operators consist of typical integer arithmetic, bitwise operations and floating point arithmetic.\u003C\u002Fp>\u003Cp>We intentionally do not implement constructs such as loops or gotos. Absence of these constructs makes it trivial to translate this intermediate language to equivalent operations in other specification languages, SMT, or provers.\u003C\u002Fp>\u003Cp>Expressions to compute memory addresses are restricted to a sum of terms, where each term consists of a single register, shifted right by a constant, and then multiplied by a constant. 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0.66 -0.143 0.847l -0.143 0.869c -0.165 0.572 -0.572 0.99 -1.221 1.243c 0.836 0.242 1.793 0.836 1.793 1.782Z m -1.551 1.089c 0.231 -0.209 0.352 -0.572 0.352 -1.089c 0 -0.418 -0.11 -0.77 -0.319 -1.067c -0.253 -0.341 -0.748 -0.517 -1.507 -0.517h -1.166v 2.772c 0 0.231 0.066 0.352 0.198 0.363c 0.077 0.011 0.286 0.022 0.638 0.022c 0.869 0 1.32 -0.033 1.804 -0.484Z \">\u003C\u002Fpath>\u003C\u002Fsymbol>\u003Csymbol id=\"gF0E6A7445930FE4169B4B41AB2DE3844\" overflow=\"visible\">\u003Cpath d=\"M 0 0m 4.411 0c 0.979 0 1.782 0.374 2.431 1.133c 0.627 0.715 0.935 1.573 0.935 2.563c 0 1.012 -0.308 1.892 -0.913 2.629c -0.649 0.792 -1.474 1.188 -2.453 1.188h -4.026v -0.429h 0.308c 0.385 0 0.616 -0.033 0.693 -0.088c 0.077 -0.055 0.121 -0.176 0.121 -0.374v -5.731c 0 -0.198 -0.044 -0.33 -0.121 -0.385c -0.077 -0.055 -0.308 -0.077 -0.693 -0.077h -0.308v -0.429Z m -0.297 0.429h -1.1c -0.429 0 -0.484 -0.011 -0.484 0.385v 5.885c 0 0.396 0.055 0.385 0.484 0.385h 1.089c 0.814 0 1.463 -0.33 1.947 -0.99c 0.363 -0.517 0.55 -1.309 0.55 -2.398c 0 -1.925 -0.726 -3.267 -2.486 -3.267Z \">\u003C\u002Fpath>\u003C\u002Fsymbol>\u003C\u002Fdefs>\u003C\u002Fsvg>\u003Cp>\u003Cem>\u003Cstrong>Figure 1:\u003Cspan style=\"white-space: pre-wrap\"> \u003C\u002Fspan>\u003C\u002Fstrong> The grammar of \u003Cspan style=\"font-variant-caps: small-caps\">Sem86\u003C\u002Fspan>′s semantics. By keeping the grammar simple, it is easier to implement translation to other languages such as LLVM IR or SMT-LIB.\u003C\u002Fem>\u003C\u002Fp>\u003C\u002Ffigure>\u003Cfigure>\u003Cdiv>\u003Cdiv>Example 3\u003C\u002Fdiv>\u003Cdiv>\u003Cp>We show the semantics for the \u003Ccode>IMUL\u003C\u002Fcode> instruction in \u003Ca href=\"#loc-4\">Figure 2\u003C\u002Fa>. There are two placeholders that depend on the output of instruction decoding: “\u003Ccode><a>\u003C\u002Fcode>” and “\u003Ccode><b>\u003C\u002Fcode>”. These will be substituted with the register corresponding to the value of the respective parts.\u003C\u002Fp>\u003Cfigure id=\"loc-4\">\u003Cpre>\u003Ccode data-lang=\"sem86\">tmp0 \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> \u003Cspan style=\"color: #4b69c6\">Mul\u003C\u002Fspan>(\u003Cspan style=\"color: #4b69c6\">SignExt\u003C\u002Fspan>[\u003Cspan style=\"color: #b60157\">32\u003C\u002Fspan>](\u003Cspan style=\"color: #d73948\"><a>\u003C\u002Fspan>), \u003Cspan style=\"color: #4b69c6\">SignExt\u003C\u002Fspan>[\u003Cspan style=\"color: #b60157\">32\u003C\u002Fspan>](\u003Cspan style=\"color: #d73948\"><b>\u003C\u002Fspan>))\n\u003Cspan style=\"color: #d73948\"><a>\u003C\u002Fspan> \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> tmp0\ntmp1 \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> \u003Cspan style=\"color: #4b69c6\">And\u003C\u002Fspan>(tmp0, \u003Cspan style=\"color: #b60157\">0xFFFFFFFF80000000\u003C\u002Fspan>)\ntmp2 \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> \u003Cspan style=\"color: #4b69c6\">Xor\u003C\u002Fspan>(tmp1, \u003Cspan style=\"color: #b60157\">0xFFFFFFFF80000000\u003C\u002Fspan>)\ntmp3 \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> \u003Cspan style=\"color: #4b69c6\">ite\u003C\u002Fspan>(tmp1, tmp2, tmp1)\n\u003Cspan style=\"color: #4b69c6\">Flag\u003C\u002Fspan>(\u003Cspan style=\"color: #d73948\">CF\u003C\u002Fspan>) \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> \u003Cspan style=\"color: #4b69c6\">ite\u003C\u002Fspan>(tmp3, \u003Cspan style=\"color: #b60157\">0x1\u003C\u002Fspan>, \u003Cspan style=\"color: #b60157\">0x0\u003C\u002Fspan>)\n\u003Cspan style=\"color: #4b69c6\">Flag\u003C\u002Fspan>(\u003Cspan style=\"color: #d73948\">OF\u003C\u002Fspan>) \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> \u003Cspan style=\"color: #4b69c6\">Flag\u003C\u002Fspan>(\u003Cspan style=\"color: #d73948\">CF\u003C\u002Fspan>)\n\u003Cspan style=\"color: #4b69c6\">Flag\u003C\u002Fspan>(\u003Cspan style=\"color: #d73948\">AF\u003C\u002Fspan>) \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> \u003Cspan style=\"color: #b60157\">0x0\u003C\u002Fspan>\n\u003Cspan style=\"color: #4b69c6\">Flag\u003C\u002Fspan>(\u003Cspan style=\"color: #d73948\">SF\u003C\u002Fspan>) \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> \u003Cspan style=\"color: #4b69c6\">SelectBit\u003C\u002Fspan>(\u003Cspan style=\"color: #b60157\">31\u003C\u002Fspan>)(tmp0)\n\u003Cspan style=\"color: #4b69c6\">Flag\u003C\u002Fspan>(\u003Cspan style=\"color: #d73948\">PF\u003C\u002Fspan>) \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> \u003Cspan style=\"color: #4b69c6\">Parity\u003C\u002Fspan>(tmp0)\ntmp4 \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> \u003Cspan style=\"color: #4b69c6\">And\u003C\u002Fspan>(tmp0, \u003Cspan style=\"color: #b60157\">0xFFFFFFFF\u003C\u002Fspan>)\n\u003Cspan style=\"color: #4b69c6\">Flag\u003C\u002Fspan>(\u003Cspan style=\"color: #d73948\">ZF\u003C\u002Fspan>) \u003Cspan style=\"color: #d73948\">:=\u003C\u002Fspan> \u003Cspan style=\"color: #4b69c6\">IsZero\u003C\u002Fspan>(tmp4)\u003C\u002Fcode>\u003C\u002Fpre>\u003Cp>\u003Cem>\u003Cstrong>Figure 2:\u003Cspan style=\"white-space: pre-wrap\"> \u003C\u002Fspan>\u003C\u002Fstrong> The semantics for the IMUL instruction operating on two 32-bit register operands. First, the product is computed and stored in \u003Ccode>tmp0\u003C\u002Fcode> and copied to destination register \u003Ccode>a\u003C\u002Fcode>. Next, all flags are updated. Updates to the AF, SF, PF and ZF are undefined. In this example, the flags are updated to reflect the result of the multiplication.\u003C\u002Fem>\u003C\u002Fp>\u003C\u002Ffigure>\u003C\u002Fdiv>\u003C\u002Fdiv>\u003C\u002Ffigure>\u003Cp>The semantics for each instruction also store control-flow behavior. Control-flow behavior can be sequential, relative near jumps, and semantics-defined jumps. Sequential means that the program counter is incremented by the instruction length. Relative near jumps add a constant offset to the program counter. Optionally, adding this constant offset can be conditional on a value computed by the semantics. Semantics-defined jumps indicate that the program counter is updated by the semantics in a non-standard way. These are used to implement operations such as jumps to absolute offsets or long jumps.\u003C\u002Fp>\u003Cp>Having this control-flow information available in a format that does not require analysis of the semantics themselves, makes it easy to determine the control flow of instructions. This is used, for example, to accurately determine the next instruction after a conditional jump. Without explicit control-flow information, we would have to inspect the program counter after each instruction to determine whether the jump was taken or not. However, since the control-flow behavior explicitly defines what the condition for taking the jump is, we can use this condition instead, which allows for more performant code generation.\u003C\u002Fp>\u003Ch3>3.2 Instruction Execution\u003C\u002Fh3>\u003Cp>The basic execution loop of \u003Cspan style=\"font-variant-caps: small-caps\">Sem86\u003C\u002Fspan> is a cached interpreter. When new instructions are executed, they are stored in a cache data structure as a tuple of a function pointer to the instruction execution function and a decoded representation of the instruction bitstring.\u003C\u002Fp>\u003Cp>The instruction execution function is compiled by translating the instruction semantics to LLVM IR, and compiling it with LLVM. This generates functions that are similar to the manual implementations found in Bochs [\u003Ca href=\"\u002Fpublications\u002Fsem86-qrs26\u002F06-bibliography#loc-5\" role=\"doc-biblioref\">7\u003C\u002Fa>]. In our current implementation these functions are compiled on-the-fly, but could also be compiled ahead of time.\u003C\u002Fp>\u003Cp>The cache data structure also contains a pointer to the instruction that will be executed next. This means that typically, no page walk, memory read, or instruction decode is necessary to determine which instruction to execute next. Executing the next instruction typically only requires following a pointer and an indirect call to the function pointer of the instruction execution function.\u003C\u002Fp>\u003Cp>There are two conditions under which the cache becomes invalid: memory may be overwritten, or page mappings may change. We handle both of these conditions with page granularity.\u003C\u002Fp>\u003Cp>Unlike many other architectures, x86 does not require the use of an instruction cache invalidation instruction to indicate that the instruction cache should be cleared. Instead, it is expected that any memory writes are immediately reflected in the instruction cache. When a page containing cached instructions is written, we mark it as ‘dirty’. For dirty pages, the cache re-verifies memory contents for every executed instruction. This ensures that changed instructions are detected immediately.\u003C\u002Fp>\u003Cp>When page mappings change, physical memory may have moved to different logical addresses. On x86, operating systems are required to explicitly signal that page mappings have changed by executing specific instructions. When this happens, we clear cached pointers to instructions on any page that has changed. This means that the execution loop will re-walk the page table to redetermine the correct pointer. Pointers between instructions on the same page can remain unchanged, as a page mapping always maps an entire page.\u003C\u002Fp>\u003Ch4>3.2.1 Memory\u003C\u002Fh4>\u003Cp>We implement the \u003Cem>fast memory\u003C\u002Fem> technique. This technique uses the host’s MMU to accelerate memory accesses. When starting, we pre-allocate an entire 4 GiB memory region and a metadata array. The allocated memory region covers the entire x86 instruction space. This means that if the correct memory is mapped into the allocated memory region, a memory access could be performed by simply adding the emulated address to the start of the memory region. The metadata array contains flags for each page, that indicate whether memory reads and writes can be performed directly on the mapped memory region. When memory needs to be mapped at a certain location, we use \u003Ccode>mmap\u003C\u002Fcode> to place memory at the right location inside the 4 GiB memory region and update the metadata.\u003C\u002Fp>\u003Cp>For often-executed code pages, we rely on \u003Cem>just-in-time\u003C\u002Fem> (JIT) code generation to compile sequences of instructions into native code. We choose page-wide code generation because this allows for simple cache invalidation. Assuming code pages are not written, they can only be moved in their entirety through page remapping. This means that, although the code on the page may be moved to a different memory location in its entirety, the instructions on a single page, as well as relative jumps, will remain the same.\u003C\u002Fp>\u003Ch4>3.2.2 JIT\u003C\u002Fh4>\u003Cp>For JIT code generation, we use off-the-shelf LLVM. LLVM compilation is too slow to be executed in the main execution loop, so compilation is instead done on dedicated threads. The semantics of all instructions in a sequence are concatenated and transformed to LLVM IR, which is then compiled to a single function by LLVM. For jumps to other instructions on the same page, we generate inline tail calls. This avoids the overhead of the cache lookup in the interpreter loop.\u003C\u002Fp>\u003Ch3>3.3 Bisection and save states\u003C\u002Fh3>\u003Cp>Bisection consists of performing a binary search over some search space, for example the number of instructions executed, to find the point where a change in execution occurs\u003Cspan id=\"loc-5\" style=\"display: inline-block; width: 0em\"> \u003C\u002Fspan>\u003Csup role=\"doc-noteref\">\u003Ca href=\"#loc-6\">1\u003C\u002Fa>\u003C\u002Fsup>. In Section \u003Ca href=\"\u002Fpublications\u002Fsem86-qrs26\u002F04-evaluation#loc-1\">Section 4\u003C\u002Fa> we use it to analyze a toy malware sample that attempts to detect whether it is running in an emulator using undefined behavior of instructions.\u003C\u002Fp>\u003Cp>The speed of bisection depends on how quickly one can determine whether a certain point in the search space exhibits the bug or not. If a full operating system needs to boot before being able to determine this, it can take a long time to search through billions of instruction executions.\u003C\u002Fp>\u003Cp>\u003Cspan style=\"font-variant-caps: small-caps\">Sem86\u003C\u002Fspan> implements \u003Cem>save states\u003C\u002Fem>, i.e., capturing and storing the current CPU, memory, and system hardware state. This save state can then be stored to memory or disk, and be used later on to resume execution. The save states can be configured to also include any changes written to disk. This allows save states to be used to rewind back to an earlier point in time.\u003C\u002Fp>\u003Cp>Since save states can rewind execution to earlier points in time, save states can be used to speed up bisection. Rather than restarting the emulator from scratch, bisection can resume from a save state.\u003C\u002Fp>\u003Csection role=\"doc-endnotes\">\u003Col style=\"list-style-type: none\">\u003Cli id=\"loc-6\">\u003Csup role=\"doc-backlink\">\u003Ca href=\"#loc-5\">1\u003C\u002Fa>\u003C\u002Fsup>We borrow this term from software engineering \u003Cspan id=\"loc-7\">[\u003C\u002Fspan>\u003Ca href=\"\u002Fpublications\u002Fsem86-qrs26\u002F06-bibliography#loc-22\" role=\"doc-biblioref\">24\u003C\u002Fa>], where bisection is typically used to identify which change introduced a bug, for example with \u003Ccode>git bisect\u003C\u002Fcode>.\u003C\u002Fli>\u003C\u002Fol>\u003C\u002Fsection>",{},{"url":48,"title":49},"\u002Fpublications\u002Fsem86-qrs26\u002F04-evaluation","Evaluation","\u002Fpublications\u002Fsem86-qrs26\u002F03-implementation",{"url":52,"title":53},"\u002Fpublications\u002Fsem86-qrs26\u002F02-related-work","Related Work",{"title":42},"publications\u002Fsem86-qrs26\u002F03-implementation","S_mROw76LASiBRUUpMnib3talHiKgi2lJttslVvrdzs",1787086053581]